View CS552526_1580454.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5525 cs5526 16-bit/20-bit multi-range adc with 4-bit latch features l delta-sigma a/d converter - linearity error: 0.0015%fs - noise free resolution: 18-bits l bipolar/unipolar input ranges - 25 mv, 55 mv, 100 mv, 1 v, 2.5 v and 5 v l chopper stabilized instrumentation amplifier l on-chip charge pump drive circuitry l 4-bit output latch l simple three-wire serial interface - spi? and microwire? compatible - schmitt trigger on serial clock (sclk) l programmable output word rates - 3.76 hz to 202hz (xin = 32.768 khz) - 11.47 hz to 616 hz (xin = 100 khz) l output settles in one conversion cycle l simultaneous 50/60 hz noise rejection l system and self-calibration with read/write registers l single +5 v analog supply +3.0 v or +5 v digital supply l low power mode consumption: 4 mw - 1.8 mw in 1 v, 2.5 v, and 5 v input ranges general description the 16-bit cs5525 and the 20-bit cs5526 are highly in- tegrated ds a/d converters which include an instrumentation amplifier, a pga (programmable gain amplifier), eight digital filters, and self and system cali- bration circuitry. the converters are designed to provide their own nega- tive supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals 100 mv. by directly supplying nbv with -2.5 v and with va+ at 5 v, 2.5 v signals (with respect to ground) can be measured. the digital filters provide programmable output update rates between 3.76 hz to 202 hz (xin = 32.768 khz). output word rates can be increased by approximately 3x by using xin = 100 khz. each filter is designed to settle to full accuracy for its output update rate in one conver- sion cycle. the filters with word rates of 15 hz or less (xin = 32.768 khz) reject both 50 and 60 hz ( 3 hz) line interference simultaneously. low power, single conversion settling time, programma- ble output rates, and the ability to handle negative input signals make these single supply products ideal solu- tions for isolated and non-isolated applications. ordering information see page 26. ain+ ain- + - x20 programmable gain va+ agnd vref+ vref- vd+ dgnd xin xout sdo sdi nbv a0 a1 a2 a3 latch differential digital filter calibration register control register output register 4th order delta-sigma modulator calibration memory calibration m c clock gen. sclk cs cpd jan 98 ds202f1
cs5525 cs5526 2 ds202f1 analog characteristics (t a = 25 c; va+, vd+ = 5 v 5%; vref+ = 2.5 v, vref- = agnd, nbv = -2.1 v, fclk = 32.768 khz, owr (output word rate) = 15 hz, bipolar mode, input range = 100 mv; see notes 1 and 2.) notes: 1. applies after system calibration at any temperature within -40 c ~ +85 c. 2. specifications guaranteed by design, characterization, and/or test. 3. specification applies to the device only and does not include any effects by external parasitic thermocouples. lsb = lsb 16 for the cs5525, and lsb 20 for the cs5526. 4. drift over specified temperature range after calibration at power-up at 25 c. 5. see the section of the data sheet which discusses input models on page 15. rms noise (notes 6 and 7) notes: 6. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 7. for peak-to-peak noise multiply by 6.6 for all ranges and output rates. 8. for input ranges <100 mv and output word rates >60 hz, 32.768 khz chopping frequency is used. specifications are subject to change without notice. parameter cs5525 cs5526 min typ max min typ max unit accuracy linearity error - 0.0015 0.003 - 0.0007 0.0015 %fs no missing codes 16 - - 20 - - bits bipolar offset (note 3) - 12 - 16 32 lsb unipolar offset (note 3) - 2 4- 3 2 64 lsb offset drift (notes 3 and 4) - 20 - - 20 - nv/c bipolar gain error - 8 31 - 8 31 ppm unipolar gain error - 16 62 - 16 62 ppm gain drift (note 4) - 1 3 - 1 3 ppm/c voltage reference input range (vref+) - (vref-) 1 2.5 3.0 1 2.5 3.0 v common mode rejection dc 50, 60 hz - - 110 130 - - - - 110 130 - - db db input capacitance - 16 - - 16 - pf cvf current (note 5) - 0.6 - - 0.6 - a/v output rate (hz) -3 db filter frequency input range, (bipolar/unipolar mode) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 3.76 3.27 90 nv 90 nv 130 nv 1.0 v 2.0 v 4.0 v 7.51 6.55 110 nv 130 nv 190 nv 1.5 v 3.0 v 7 v 15.0 12.7 170 nv 200 nv 250 nv 2.0 v 5.0 v 10 v 30.1 25.4 250 nv 300 nv 500 nv 4.0 v 10 v 15 v 60.0 50.4 500 nv 1.0 v 1.5 v 15 v 45 v 85 v 123.2 (note 8) 103.6 2.0 v 4.0 v 8.0 v 72 v 190 v 350 v 168.9 (note 8) 141.3 10 v 20.0 v 30 v 340 v 900 v 2.0 mv 202.3 (note 8) 169.2 30 v 55 v 105 v 1.1 mv 2.4 mv 5.3 mv
cs5525 cs5526 ds202f1 3 analog characteristics (continued) notes: 9. the minimum full scale calibration range (fscr) is limited by the maximum allowed gain register value (with margin). the maximum fscr is limited by the ds modulators 1s density range. 10. the maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 11. all outputs unloaded. all input cmos levels. parameter min typ max unit analog input common mode + signal on ain+ or ain- bipolar/unipolar mode nbv = -1.8 to -2.5 v range = 25 mv, 55 mv, or 100 mv range = 1 v, 2.5 v, or 5 v nbv = agnd range = 25 mv, 55 mv, or 100 mv range = 1 v, 2.5 v, or 5 v -0.150 nbv 1.85 0.0 - - - - 0.950 va+ 2.65 va+ v v v v common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance - 10 - pf cvf current on ain+ or ain- (note 5) range = 25 mv, 55 mv, or 100 mv range = 1 v, 2.5 v, or 5 v - - 100 1.2 300 - pa a/v system calibration specifications full scale calibration range bipolar/unipolar mode (note 9) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 17.5 38.5 70 0.70 1.75 3.50 - - - - - - 32.5 71.5 105 1.30 3.25 va+ mv mv mv v v v offset calibration range bipolar/unipolar mode 25 mv 55 mv 100 mv (note 10) 1 v 2.5 v 5 v - - - - - - - - - - - - 12.5 27.5 50 0.5 1.25 2.50 mv mv mv v v v power supplies dc power supply currents (normal mode) i a+ i d+ i nbv - - - 1.3 15 400 1.7 30 550 ma a a power consumption normal mode (note 11) low power mode standby sleep - - - - 7.5 4.0 1.2 500 10 6.5 - - mw mw mw w power supply rejection dc positive supplies dc nbv - - 95 110 - - db db
cs5525 cs5526 4 ds202f1 5 v digital characteristics (t a = 25 c; va+, vd+ = 5 v 5%; gnd = 0; see notes 2 and 12.)) notes: 12. all measurements performed under static conditions. 13. i out = -100 a unless stated otherwise. (v oh = 2.4 v @ i out = -40 a.) 3.0 v digital characteristics (t a = 25 c; va+ = 5 v 5%; vd+ = 3.0 v 10%; gnd = 0; see notes 2 and 12.)) parameter symbol min typ max unit high-level input voltage all pins except xin and sclk xin sclk v ih 0.6 vd+ 3.5 (vd+) - 0.45 - - - - vd+ - v v v low-level input voltage all pins except xin and sclk xin sclk v il - 0.0 - - - - 0.8 1.5 0.6 v v v high-level output voltage all pins except cpd and sdo (note 13) cpd, i out = -4.0 ma sdo, i out = -5.0 ma v oh (va+) - 1.0 (vd+) - 1.0 (vd+) - 1.0 - - - - - - v v v low-level output voltage all pins except cpd and sdo, i out = 1.6 ma cpd, i out = 2 ma sdo, i out = 5.0 ma v ol - - - - - - 0.4 0.4 0.4 v v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit high-level input voltage all pins except xin and sclk xin sclk v ih 0.6 vd+ 0.54 va+ (vd+) - 0.45 - - - - vd+ - v v v low-level input voltage all pins except xin and sclk xin sclk v il - 0.0 - - - - 0.16 vd+ 1.5 0.6 v v v high-level output voltage all pins except cpd and sdo, i out = -400 a cpd, i out = -4.0 ma sdo, i out = -5.0 ma v oh (va+) - 0.3 (vd+) - 1.0 (vd+) - 1.0 - - - - - - v v v low-level output voltage all pins except cpd and sdo, i out = 400 a cpd, i out = 2 ma sdo, i out = 5.0 ma v ol - - - - - - 0.3 0.4 0.4 v v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf
cs5525 cs5526 ds202f1 5 dynamic characteristics recommended operating conditions (agnd, dgnd = 0 v; see note 14.)) notes: 14. all voltages with respect to ground. absolute maximum ratings (agnd, dgnd = 0 v; see note 14.) notes: 15. no pin should go more negative than nbv - 0.3 v. 16. applies to all pins including continuous overvoltage conditions at the analog input (ain) pins. 17. transient current of up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 18. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol ratio unit modulator sampling frequency f s xin/2 hz filter settling time to 1/2 lsb (full scale step) t s 1/f out s parameter symbol min typ max unit dc power supplies positive digital positive analog vd+ va + 2.7 4.75 5.0 5.0 5.25 5.25 v v analog reference voltage (vref+) - (vref-) vref diff 1.0 2.5 3.0 v negative bias voltage nbv -1.8 -2.1 -2.5 v parameter symbol min max unit dc power supplies (note 15) positive digital positive analog vd+ va + -0.3 -0.3 +6.0 +6.0 v v negative bias voltage negative potential nbv +0.3 -3.0 v input current, any pin except supplies (note 16 and 17) i in -10ma output current i out -25ma power dissipation (note 18) pdn - 500 mw analog input voltage vref pins ain pins v inr v ina -0.3 nbv - 0.3 (va+) + 0.3 (va+) + 0.3 v v digital input voltage v ind -0.3 (vd+) + 0.3 v ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c
cs5525 cs5526 6 ds202f1 switching characteristics (t a = 25 c; va+ = 5 v 5%; vd+ = 3.0 v 10% or 5 v 5%; input levels: logic 0 = 0 v, logic 1 = vd+; c l = 50 pf.)) notes: 19. device parameters are specified with a 32.768 khz clock; however, clocks up to 100 khz can be used for increased throughput. 20. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 21. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. 22. applicable when sclk is continuously running. parameter symbol min typ max unit master clock frequency (note 19) internal clock external clock xin 30 30 32.768 32.768 36 100 khz master clock duty cycle 40 - 60 % rise times (note 20) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 20) any digital input except sclk sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 32.768 khz (note 21) t ost - 500 - ms power-on reset period t por - 1003 - xin cycles serial port timing serial clock frequency sclk 0 - 2 mhz sclk falling to cs falling for continuous running sclk (note 22) t 0 100 - - ns serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to valid latch clock t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 - - 150 ns sclk falling to new data bit t 8 - - 150 ns cs rising to sdo hi-z t 9 - - 150 ns
cs5525 cs5526 ds202f1 7 cs sclk t 0 t 2 t 1 t 3 t 6 continuous running sclk timing (not to scale) cs sclk msb msb-1 lsb sdi t 3 t 4 t 5 t 1 t 2 t 6 sdi write timing (not to scale) cs sclk msb msb-1 lsb sdo t 7 t 8 t 1 t 2 t 9 sdo read timing (not to scale)
cs5525 cs5526 8 ds202f1 general description the cs5525 and cs5526 are 16-bit and 20-bit pin compatible converters which include a chopper- stabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. they are both optimized for measuring low-level unipolar or bipolar signals in process control and medical ap- plications. the cs5525/26 also include a fourth order delta- sigma modulator, a calibration microcontroller, eight digital filters, a 4-bit analog latch, and a serial port. the digital filters provide any one of eight different output update rates. the cs5525/26 include a cpd (charge pump drive) output (shown in figure 1). cpd provides a negative bias voltage to the on-chip instrumenta- tion amplifier when used with a combination of ex- ternal diodes and capacitors. this enables the cs5525/26 to measure negative voltages with re- spect to ground, making the converters ideal for thermocouple temperature measurements. theory of operation the cs5525/26 a/d converters are designed to op- erate from a single +5 v analog supply and provide several different input ranges. see the analog characteristics section on page 3 for details. figure 1 illustrates the cs5525/26 connected to generate their own negative bias supply using the on-chip cpd (charge pump drive). this enables the cs5525/26 to measure ground referenced sig- nals with magnitudes down to nbv (negative bias voltage, approximately -2.1 v in this example). figure 2 illustrates a charge pump circuit when the converters are powered from a +3.0 v digital sup- ply. alternatively, the negative bias supply can be generated from a negative supply voltage or a resis- tive divider as illustrated in figure 3. xout vd+ va+ vref+ vref- dgnd nbv ain+ sclk sdo sdi cs5525 xin cpd cs 10 w +5v analog supply 0.1 m f0.1 m f 20 19 3 1 agnd 213 10 9 11 14 17 18 12 5 optional clock source serial data interface 8 32.768 ~ 100 khz 2.5v up to 100 mv input ain- 4 10 k w 0.1 m f note: cold-junction measurement is performed by a second a/d or via a multiplexer. 10 m f 0.015 m f 1n4148 1n4148 + bav199 16 a3 15 a2 7 a1 6 a0 charge-pump network for vd+ = 5v only and xin = 32.768 khz. cs5526 * 5m w * optional, see charge pump drive section. logic outputs: a0 - a3 switch from va+ to agnd. 10 k w figure 1. cs5525/26 configured to use on-chip charge pump to supply nbv.
cs5525 cs5526 ds202f1 9 figure 4 illustrates the cs5525/26 connected to measure ground referenced unipolar signals of a positive polarity using the 1 v, 2.5 v, and 5 v input voltage ranges on the converter. for the 25 mv, 55 mv, and 100 mv ranges the signal must have a common mode near +2.5 v (nbv = 0v). the cs5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. figure 5 illustrates the cs5525/26 connected to measure the output of a ratiometric differential bridge transducer while op- erating from a single +5 v supply. -5v nbv 30.1k 34.8k 2n5087 or similar -5v 2.1k 2.0k nbv + 10 m f 10 m f + figure 2. charge pump drive circuit for vd+ = 3 v. figure 3. alternate nbv circuits. xout vd+ va+ vref+ vref- dgnd nbv ain+ ain- sclk sdo sdi cs5525 xin cpd cs 10 w +5v analog supply 0.1 m f 0.1 m f 20 19 3 4 1 agnd 213 10 9 11 14 17 18 12 5 optional clock source serial data interface 8 32.768 ~ 100 khz 2.5v 0 to +5v input cs5526 16 a3 15 a2 7 a1 6 a0 + - cm = 0 to va+ figure 4. cs5525/26 configured for ground-referenced unipolar signals.
cs5525 cs5526 10 ds202f1 system initialization when power to the cs5525/26 is applied, they are held in a reset condition until their 32.768 khz os- cillators have started and their start-up counter-tim- er elapses. due to the high q of a 32.768 khz crystal, the oscillators take 400-600 ms to start. the converters counter-timer counts no more than 1024 oscillator clock cycles to make sure the oscil- lator is fully stable. during this time-out period the serial port logic is reset and the rv (reset valid) bit in the configuration register is set. a reset can be initiated at any time by writing a logic 1 to the rs (reset system) bit in the configuration register. this automatically sets the rv bit until the rs bit is written to logic 0, and the configuration register is read. after a reset, the on-chip registers are ini- tialized to the following states and the converters are ready to perform conversions. command operation the cs5525/26 include a microcontroller with five registers used to control the converter. each regis- ter is 24-bits in length except the 8-bit command register (command, configuration, offset, gain, and conversion data). after a system initialization or re- set, the serial port is initialized to the command mode and the converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). table 1 lists all the valid com- mands. once a valid 8-bit command (a read or a write command word) is received and interpreted by the command register, the serial port enters the data mode. in data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if set-up register is selected). see table 2 for configuring the cs5525/26. xout vd+ va+ vref+ vref- dgnd nbv ain+ ain- sclk sdo sdi cs5525 xin cpd cs 10 w +5v analog supply 0.1 m f 0.1 m f + - 20 19 3 4 1 agnd 213 10 9 11 14 17 18 12 5 optional clock source serial data interface 30mv f.s. 8 32.768 ~ 100khz 16 a3 15 a2 7 a1 6 a0 cs5526 figure 5. cs5525/26 configured for single supply bridge measurement. configuration register: 000040(h) offset register: 000000(h) gain register: 800000(h)
cs5525 cs5526 ds202f1 11 reading/writing on-chip registers the cs5525/26s offset, gain, and configuration registers are read/writable while the conversion data register is read only. to perform a read from a specific register, the r/w bit of the command word must be a logic 1. the sc, cc, and ps/r bits must be logic 0 and the cb (msb) bit must be a logic 1. the register to be writ- ten is selected with the rsb2-rsb0 bits of the command word. to perform a write to a specific register, the r/w bit of the command word must be a logic 0. the sc, cc, and ps/r bits must be logic 0 and the cb (msb) bit must be a logic 1. the register to be written is se- lected with the rsb2-rsb0 bits of the command word. figure 6 illustrates the serial sequence neces- sary to write to, or read from the serial port. if the set-up registers are chosen with the rsb2- rsb0 bits, the registers are read or written in the following sequence: offset, gain and configura- tion. this is accomplished by following one 8-bit command word with three 24-bit data words for a total of 72 data bits. command register d7(msb)d6d5d4d3d2d1d0 cb sc cc r/w rsb2 rsb1 rsb0 ps/r bit name value function d7 command bit, cb 0 1 null command (no operation). all command bits, including cb must be 0. logic 1 for executable commands. d6 single conversion, sc 0 1 single conversion not active. perform a conversion. d5 continuous conversions, cc 0 1 continuous conversions not active. perform conversions continuously. d4 read/write , r/w 0 1 write to selected register. read from selected register. d3-d1 register select bit, rsb2-rsb0 000 001 010 011 100 101 110 111 offset register gain register configuration register conversion data register (read only) set-up registers (offset, gain, configuration) reserved reserved reserved d0 power save/run , ps/r 0 1 run power save table 1. command set
cs5525 cs5526 12 ds202f1 c on fi gurat i on reg i ster * r indicates the bit value after the part is reset d23(msb) d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 a3 a2 a1 a0 nu cfs nu lpm wr2 wr1 wr0 u/b d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 g2 g1 g0 pd rs rv pf pss df cc2 cc1 cc0 bit name value function d23-d20 latch outputs, a3-a0 0000 r* latch output pins a3-a0 mimic the d23-d20 register bits. d19 not used, nu 0 r must always be logic 0. d18 chop frequency select, cfs 0 1 r 256 hz amplifier chop frequency 32768 hz amplifier chop frequency d17 not used, nu 0 r must always be logic 0. d16 low power mode, lpm 0 1 r normal mode reduced power mode d15-d13 word rate, wr2-0 note: for xin = 32.768khz 000 001 010 011 100 101 110 111 r 15.0 hz (2182 xin cycles) 30.1 hz (1090 xin cycles) 60.0 hz (546 xin cycles) 123.2 hz (266 xin cycles) 168.9 hz (194 xin cycles) 202.3 hz (162 xin cycles) 3.76 hz (8722 xin cycles) 7.51 hz (4362 xin cycles) d12 unipolar/bipolar , u/b 0 1 r bipolar measurement mode unipolar measurement mode d11-d9 gain bits, g2-g0 000 001 010 011 100 101 110/111 r 100 mv (assumes vref = 2.5v) 55 mv 25 mv 1v 5.0 v 2.5 v not used. d8 pump disable, pd 0 1 r charge pump enabled for pd = 1, the cpd pin goes to a hi-z output state. d7 reset system, rs 0 1 r normal operation activate a reset cycle. to return to normal operation write bit to zero. d6 reset valid , rv 0 1r no reset has occurred or bit has been cleared (read only). valid reset has occurred. (cleared when read.) d5 port flag, pf 0 1 r port flag mode inactive port flag mode active d4 power save select, pss 0 1 r standby mode (oscillator active, allows quick power-up) sleep mode (oscillator inactive) d3 done flag, df 0 1 r done flag bit is cleared (read only). calibration or conversion cycle completed (read only). d2-d0 calibration control bits, cc2-cc0 000 001 010 011 100 101 110 111 r normal operation (no calibration) offset -- self-calibration gain -- self-calibration offset self-calibration followed by gain self-calibration not used. offset -- system calibration gain -- system calibration not used. table 2. configuration register
cs5525 cs5526 ds202f1 13 command time 8 sclks data time 24 sclks (or 72 sclks for set-up registers) write cycle cs sclk sdi msb lsb command time 8 sclks cs sclk sdi data time 24 sclks (or 72 sclks for set-up registers) read cycle sdo msb lsb command time 8 sclks 8 sclks clear sdo flag sdo continuous conversion read (pf bit = 1) sdo sclk sdi t * d data time 24 sclks msb lsb * td = xin/owr clock cycles for each conversion except the first conversion which will take xin/owr + 7 clock cycles xin/owr clock cycles figure 6. command and data word timing.
cs5525 cs5526 14 ds202f1 analog input figure 7 illustrates a block diagram of the analog in- put signal path inside the cs5525/26. the front end consists of a chopper-stabilized instrumentation am- plifier with 20x gain and a programmable gain sec- tion. the instrumentation amplifier is powered from va+ and from the nbv (negative bias voltage) pin allowing the cs5525/26 to be operated in either of two analog input configurations. the nbv pin can be biased to a negative voltage between -1.8 v and -2.5 v, or tied to agnd. the choice of the operating mode for the nbv voltage depends upon the input signal and its common mode voltage. for the 25 mv, 55 mv, and 100 mv input ranges, the input signals to ain+ and ain- are amplified by the 20x instrumentation amplifier. for ground refer- enced signals with magnitudes less then 100 mv, the nbv pin should be biased with -1.8 v to -2.5 v. if nbv is tied between -1.8 v and -2.5 v, the (com- mon mode + signal) input on ain+ and ain- must stay between -0.150 v and 0.950 v to ensure prop- er operation. alternatively, nbv can be tied to agnd where the input (common mode + signal) on ain+ and ain- must stay between 1.85 v and 2.65 v to ensure that the amplifier operates prop- erly. for the 1 v, 2.5 v, and 5 v input ranges, the instru- mentation amplifier is bypassed and the input sig- nals are directly connected to the programmable gain block. with nbv tied between -1.8 v and -2.5 v, the (common mode + signal) input on ain+ and ain- must stay between nbv and va+. alternatively, nbv can be tied to agnd where the input (common mode + signal) on ain+ and ain- pins can span the entire range between agnd and va+. the cs5525/26 can accommodate full scale ranges other than 25 mv, 55 mv, 100 mv, 1 v, 2.5 v and 5 v by performing a system calibration within the limits specified. see the calibration section for more details. another way to change the full scale range is to increase or to decrease the voltage refer- ence to other than 2.5 v. see the voltage refer- ence section for more details. three factors set the operating limits for the input span. they include: instrumentation amplifier satu- ration, modulator 1s density, and a lower reference voltage. when the 25 mv, 55 mv or 100 mv range is selected, the input signal (including the common mode voltage and the amplifier offset voltage) must not cause the 20x amplifier to saturate in ei- ther its input stage or output stage. to prevent sat- uration the absolute voltages on ain+ and ain- must stay within the limits specified (refer to the analog input table on page 3). additionally, the differential output voltage of the amplifier must not exceed 2.8 v. the equation abs(vin + vos) x 20 = 2.8 v defines the differential output limit, where vin = (ain+) - (ain-) is the differential input voltage and vos is the ab- solute maximum offset voltage for the instrumenta- tion amplifier (vos will not exceed 40 mv). if the vref+ differential 4th order delta- sigma modulator digital filter ain+ ain- programmable gain vref- nbv x20 figure 7. block diagram of analog signal path
cs5525 cs5526 ds202f1 15 differential output voltage from the amplifier ex- ceeds 2.8 v, the amplifier may saturate, which will cause a measurement error. the input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. the nominal full scale input span of the modulator (from 30 percent to 70 percent 1s density) is determined by the vref voltage divided by the gain factor. see ta- ble 3 to determine if the cs5525/26 are being used properly. for example, in the 55 mv range to de- termine the nominal input voltage to the modulator, divide vref (2.5 v) by the gain factor (2.2727). when a smaller voltage reference is used, the re- sulting code widths are smaller causing the con- verter output codes to exhibit more changing codes for a fixed amount of noise. table 3 is based upon a vref = 2.5 v. for other values of vref, the val- ues in table 3 must be scaled accordingly. figures 8 and 9 illustrate the input models for the ain and vref pins. the dynamic input current for each of the pins can be determined from the models shown and is dependent upon the setting of the cfs (chop frequency select) bit. the effective input impedance for the ain+ and ain- pins remains constant for the three low level measurement rang- es (25 mv, 55 mv, and 100 mv). the input current is lowest with the cfs bit cleared to logic 0. note: residual noise appears in the converters baseband for output word rates greater than 60 hz if cfs is logic 0. by set- ting cfs to logic 1, the amplifiers chop frequency chops at 32768 hz eliminating the residual noise, but increasing the current. note that c=48pf is for input current modeling only. for physical input capacitance see input capacitance spec- ification under analog characteristics on page 3. note: 1. the converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's maximum full scale input all scale directly with the value of the voltage reference. the values in the table assume a 2.5 v vref voltage. input range (1) max. differential output 20x amplifier vref gain factor d - s nominal (1) differential input d - s (1) max. input 25 mv 2.8 v (2) 2.5v 5 0.5 v 0.75 v 55 mv 2.8 v (2) 2.5v 2.272727... 1.1 v 1.65 v 100 mv 2.8 v (2) 2.5v 1.25 2.0 v 3.0 v 1.0 v - 2.5v 2.5 1.0 v 1.5 v 2.5 v - 2.5v 1.0 2.5 v 5.0 v 5.0 v - 2.5v 0.5 5.0 v 0v, va+ table 3. relationship between full scale input, gain factors, and internal analog signal limitations ain 25mv, 55mv, and 100mv ranges v 25mv i = fv c os os n c = 48p f cfs = 0 , f = 256 hz cfs = 1 , f = 32.768 khz ain+ 1v, 2.5 v, and 5v ranges c = 32pf i = [(v ) - (v )] fc n ain+ ain- ain- f = 32.768 khz figure 8. input models for ain+ and ain- pins vref+ c = 16pf vref- i = [(vref+) - (vref-)] fc n f = 32.768 khz figure 9. input model for vref+ and vref- pins.
cs5525 cs5526 16 ds202f1 charge pump drive the cpd (charge pump drive) pin of the convert- ers can be used with external components (shown in figure 1) to develop an appropriate negative bias voltage for the nbv pin. when cpd is used to gen- erate the nbv, the nbv voltage is regulated with an internal regulator loop referenced to va+. therefore, any change on va+ results in a propor- tional change on nbv. with va+ = 5 v, nbvs regulation is set proportional to va+ at approxi- mately -2.1 v. figure 3 illustrates a means of supplying nbv volt- age from a -5 v supply. for ground based signals with the instrumentation amplifier engaged (when in the 25mv, 55mv, or 100mv ranges), the voltage on the nbv pin should at no time be less negative than -1.8 v or more negative than -2.5 v. to pre- vent excessive voltage stress to the chip the nbv voltage should not be more negative than -3.0 v. the components in figure 1 are the preferred com- ponents for the cpd filter. however, smaller ca- pacitors can be used with acceptable results. the 10 m f ensures very low ripple on nbv. intrinsic safety requirements prohibit the use of electrolytic capacitors. in this case, two 0.47 m f ceramic capac- itors in parallel can be used. the cpd pin itself is a tri-state output and enters tri-state whenever the converters are placed into the sleep mode, standby mode, or when the charge pump is disabled (when the pump disable bit, bit d8 in the configuration register, is set). once in tri- state, the digital current can increase if this cpd output floats near 1/2 digital supply. to ensure the cpd pin stays near ground and to minimize the digital current, add a 5m w resistor between it and dgnd (see figure 1). if the resistor is left out, the digital supply current may increase from 2 m a to 10 m a. voltage reference the cs5525/26 are specified for operation with a 2.5 v reference voltage between the vref+ and vref- pins of the devices. for a single-ended ref- erence voltage, such as the lt1019-2.5, the refer- ences output is connected to the vref+ pin of the cs5525/26. the ground reference for the lt1019- 2.5 is connected to the vref- pin. the differential voltage between the vref+ and vref- can be any voltage from 1.0 v up to 3.0 v, however, the vref- pin can not go below analog ground. calibration the cs5525/26 offer five different calibration functions including self calibration and system cal- ibration. however, after the cs5525/26 are reset, they can perform measurements without being cal- ibrated. in this case, the converters will utilize the initialized values of the on-chip registers (gain = 1.0, offset = 0.0) to calculate output words for the 100 mv range. any initial offset and gain errors in the internal circuitry of the chips will remain. the gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converters transfer function. one lsb in the offset register is 2 -24 pro- portion of the input span (bipolar span is 2 times the unipolar span). the msb in the offset register de- termines if the offset to be trimmed is positive or negative (0 positive, 1 negative). the converters can typically trim 50 percent of the input span. the gain register spans from 0 to (2 - 2 -23 ). the decimal equivalent meaning of the gain register is where the binary numbers have a value of either zero or one (b 0 corresponds to the msb). refer to table 4 for details. db 0 2 0 b 1 2 1 C b 2 2 2 C ? b n 2 n C ++++ b i 2 i C i 0 = n ? ==
cs5525 cs5526 ds202f1 17 the offset and gain calibration steps each take one conversion cycle to complete. at the end of the cal- ibration step, the calibration control bits will be set back to logic 0, and the df (done flag) bit will be set to a logic 1. for the combination self-calibra- tion (cc2-cc0= 011; offset followed by gain), the calibration will take two conversion cycles to com- plete and will set the df bit after the gain calibra- tion is completed. the df bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. reading the configuration register alone will not clear the df bit. self calibration the cs5525/26 offer both self offset and self gain calibrations. for the self-calibration of offset in the 25 mv, 55 mv, and 100 mv ranges, the converter internally ties the inputs of the instrumentation am- plifier together and routes them to the ain- pin as shown in figure 10. for proper self-calibration of offset to occur in the 25 mv, 55 mv, and 100 mv ranges, the ain- pin must be at the proper com- mon-mode-voltage (i.e. ain- = 0v, nbv must be between -1.8 v to -2.5 v). for self-calibration of offset in the 1.0 v, 2.5 v, and 5 v ranges, the inputs of the modulator are connected together and then routed to the vref- pin as shown in figure 11. for self-calibration of gain, the differential inputs of the modulator are connected to vref+ and table 3. table 4. offset and gain registers offset register one lsb represents 2 -24 proportion of the input span (bipolar span is 2 times unipolar span) offset and data word bits align by msb (bit msb-4 of offset register changes bit msb-4 of data) gain register the gain register span is from 0 to (2-2 -23 ). after reset the msb = 1, all other bits are 0. msb lsb register sign 2 -2 2 -3 2 -4 2 -5 2 -6 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 reset (r) 0 00000 0 0 0 0 0 0 msb lsb register 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 reset (r) 1 00000 0 0 0 0 0 0 ? ? ain+ ain- s1 op en s2 closed + - x20 + - figure 10. self calibration of offset (low ranges). ain+ ain- s1 open + - x20 + - s2 open s4 closed vref- s3 closed figure 11. self calibration of offset (high ranges).
cs5525 cs5526 18 ds202f1 vref- as shown in figure 12. for any input range other than the 2.5 v range, the modulator gain error can not be completely calibrated out. this is due to the lack of an accurate full scale voltage internal to the chips. the 2.5 v range is an exception because the external reference voltage is 2.5 v nominal and is used as the full scale voltage. in addition, when self-calibration of gain is performed in the 25 mv, 55 mv, and 100 mv input ranges, the instrumenta- tion amplifiers gain is not calibrated. these two factors can leave the converters with a gain error of up to 20% after self-calibration of gain. there- fore, a system gain is required to get better accura- cy, except for the 2.5 v range. system calibration for the system calibration functions, the user must supply the converters calibration signals which rep- resent ground and full scale. when a system offset calibration is performed, a ground reference signal must be applied to the converter. see figures 13 and 14. as shown in figures 15 and 16, the user must input a signal representing the positive full scale point to perform a system gain calibration. in either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the system calibration specifications). ain+ ain- open + - x20 + - open closed vref+ closed vref- + - reference figure 12. self calibration of gain (all ranges). + - x20 + - external connections 0v + - ain+ ain- cm + - figure 13. system calibration of offset (low ranges). + - x20 + - external connections + - ain+ ain- cm + - 0v figure 14. system calibration of offset (high ranges). + - x20 + - external connections full scale + - ain+ ain- cm + - figure 15. system calibration of gain (low ranges) + - x20 + - external connections full scale + - ain+ ain- cm + - figure 16. system calibration of gain (high ranges).
cs5525 cs5526 ds202f1 19 assuming a system can provide two known voltag- es, equations can allow the user to manually com- pute the calibration registers values based on two uncalibrated conversions. the offset and gain cali- bration registers are used to adjust a typical conver- sion as follows: rc = (ru + co>>4) * cg / 2 23 . calibration can be performed using the following equations: co = (rc0/g - ru0) << 4 cg = 2 23 * g where g = (rc1 - rc0)/(ru1-ru0). note: uncalibrated conversions imply that the gain and offset registers are at default {gain register = 0x800000 (hex) and offset register = 0x000000 (hex)}. the variables are defined below. v0 = first calibration voltage v1 = second calibration voltage (greater than v0) ru = result of any uncalibrated conversion ru0 = result of uncalibrated conversion v0 (20- bit integer or 2s complement) ru1 = result of uncalibrated conversion of v1 (20-bit integer or 2s complement) rc = result of any conversion rc0 = desired calibration result of converting v0 (20-bit integer or 2s complement) rc1 = desired calibration result of converting v1 (20-bit integer or 2s complement) co = offset calibration register value (24-bit 2s complement) cg = gain calibration register value (24-bit integer) >> = the shift right operator (e.g. x >>2 is x shift- ed right 2 bits) << = the shift left operator (e.g. x<<2 is x shifted left 2 bits) note: the shift operators are used here to align the decimal points of words of various lengths. data to the right of the decimal point may be used in the calculations shown. for the cs5525 all conversion results (ru, rc...) are 16 bits instead of 20 bits. to get the equations to work correctly pad the 16 bit results with four zeros (on the right). calibration tips calibration steps are performed at the output word rate selected by the wr2-wr0 bits of the configu- ration register. since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. also, to minimize digital noise near the devices, the user should wait for each calibra- tion step to be completed before reading or writing to the serial port. for maximum accuracy, calibrations should be per- formed for offset and gain for each gain setting (se- lected by changing the g2-g0 bits of the configuration register). and if factory calibration is performed using the system calibration capabilities of the cs5525/26, the offset and gain register con- tents can be read by the system microcontroller and recorded in eeprom. these same calibration words can then be uploaded into the offset and gain registers of the converters when power is first ap- plied to the system, or when the gain range is changed. two final tips include two ways to determine when calibration is complete: 1) wait for sdo to fall. it falls to logic 0 if the pf (port flag) bit of the con- figuration register is set to logic 1; or 2) poll the df (done flag) bit in the configuration register which is set at completion of calibration. whichever method is used, the calibration control bits (cc2- cc0) will return to logic 0 upon completion of any calibration. limitations in calibration range system calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the analog input section of this data sheet. system calibration can also be limited by the intrinsic gain errors of the instrumentation amplifier and the modulator. for gain calibrations
cs5525 cs5526 20 ds202f1 the input signal can be reduced to the point in which the gain register reaches its upper limit of 2.0 (decimal) [ffffff hex] (this is most likely to oc- cur with an input signal approximately 1/2 the nominal range). alternatively, the input signal can be increased to a point in which the modulator reaches its ones density upper limit of 80% (this is most likely to occur with an input signal approxi- mately 1.5 times the nominal range). also, for full scale inputs larger than the nominal full scale value of the range selected, there is some voltage at which the various internal circuits may saturate due to limited amplifier headroom (this is most likely to occur on the 100 mv range setting when nbv = - 1.8 v). analog output latch pins the a3-a0 pins of the converters mimic the d23- d20 bits of the configuration register. a3-a0 can be used to control multiplexers and other logic functions outside the converter. the outputs can sink or source at least 1 ma, but it is recommended to limit drive currents to less than 20 m a to reduce self-heating of the chip. these outputs are powered from va+, hence, their output voltage for a logic 1 will be limited to the va+ voltage. serial port interface the cs5525/26 serial interface consist of four pins, sclk, sdo, sdi, and cs . the cs pin must be held low (logic 0) before sclk transitions can be recognized by the port logic. the sdo output will be held at high impedance any time cs is a logic 1. if the cs pin is tied low, the port can function as a three wire interface. the sclk input is designed with a schmitt-trigger input to allow an optoisolator with slower rise and fall times to directly drive the pin. the sdo output is capable of sinking or sourcing up to 5 ma to directly drive an optoisolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourcing 5 ma. serial port initialization the serial port is initialized to the command mode whenever a power-on reset is performed inside the converter, when the port initialization sequence is completed, or whenever a command byte, data word sequence is completed. the port initialization sequence involves clocking 15 (or more) bytes of all 1's, followed by one byte with the following bit contents (11111110). this sequence places the chips in the command mode where it waits for a valid command. performing conversions (with pf bit = 0) setting the sc (single conversion) bit of the com- mand word to a logic 1 with the cb bit = 1, all other command bits = 0, the cs5525/cs5526 will per- form one conversion. at the completion of the con- version the df (done flag) bit of the configuration register will be set to a logic 1. the user can read the configuration register to determine if the df bit is set. if df has been set, a command can be issued to read the conversion data register to obtain the conversion data word. the df bit of the configu- ration register will be cleared to logic 0 when the data register, the gain register, the offset register, or the set-up registers are read. reading only the con- figuration register will not clear the df flag bit. if an sc command is issued to the converters while they are performing a conversion, the filter will re- start a convolution cycle to perform a new conver- sion. performing conversions (with pf bit = 1) setting the pf bit of the configuration register to a logic 1 enables the sdo output pin to behave as a flag signal whenever conversions are completed. this eliminates the need for the user to read the df flag bit of the configuration register to determine if the conversion data word is available. if the sc (single conversion) command is issued (sc = 1, cb= 1, all other command bits = 0) the sdo pin will go low at the completion of a conver-
cs5525 cs5526 ds202f1 21 sion. the user would then issue 8 sclks (with sdi = logic 0) to clear the sdo flag. upon the fall- ing edge of the 8th sclk, the sdo pin will present the first bit (msb) of the conversion word. 24 sclks (high, then low) are required to read the conversion word from the port. the user must not give an explicit command to read the conversion data register when the pf bit is set to logic 1. the data conversion word must be read before a new command can be entered (if the sc command is used with pf = 1). if the cc (continuous conversion) command is is- sued (cc = 1, cb =1, all other command bits = 0) the sdo pin will go low at the completion of a con- version. the user would then issue 8 sclks (with sdi = logic 0) to clear the sdo flag. upon the fall- ing edge of the 8th sclk, the sdo pin will present the first bit (msb) of the conversion word. 24 sclks (high, then low) are required to read the conversion word from the port. the user must not give an explicit command to read the conversion data register when the pf bit is set to logic 1. when operating in the continuous conversion mode, the user need not read every conversion. if the user does nothing after sdo falls, sdo will rise one xin clock cycle before the next conversion word is available and then fall again to signal that another conversion word is available. if the user begins to clear the sdo flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is com- plete if the user wants to be able to read the new conversion data. to exit the continuous conversion mode, issue any valid command to the sdi input when the sdo flag falls. if a cc command is issued to the converter while it is performing a conversion, the filter will restart a convolution cycle to perform a new con- version. output word rate selection the wr2-wr0 bits of the configuration register set the output conversion word rate of the convert- ers as shown in table 2. the word rates indicated in the table assume a master clock of 32.768 khz. upon reset the converters are set to operate with an output word rate of 15.0 hz. clock generator the cs5525/26 include a gate which can be con- nected with an external crystal to provide the master clock for the chips. they are designed to operate us- ing a low-cost 32.768 khz tuning fork type crys- tal. one lead of the crystal should be connected to xin and the other to xout. lead lengths should be minimized to reduce stray capacitance. the converters will operate with an external (cmos compatible) clock with frequencies up to three times the typical crystal frequency of 32.768 khz. figure 17 details the converters performance at increased clock rates. the 32.768 khz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. to maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 c to +60 c). however, applications with the cs5525/26 dont generally re- quire such tight tolerances. when 32.768 khz sur- face mount crystals are used, it is recommended that protection components, an external resistor and ca- pacitor as shown in figure 18, be used. figure 17. high speed clock performance
cs5525 cs5526 22 ds202f1 digital filter the cs5525/26 have eight different linear phase digital filters which set the output word rates (owrs) as stated in table 2. these rates assume that xin is 32.768 khz. each of the filters has a magnitude response similar to that shown in figure 19. the filters are optimized to settle to full accura- cy every conversion and yield better than 80 db re- jection for both 50 and 60 hz with output word rates at or below 15.0 hz. the converters digital filters scale with xin. for example with an output word rate of 15 hz, the fil- ters corner frequency is typically 12.7 hz. if xin is increased to 64.536 khz the owr doubles and the filters corner frequency moves to 25.4 hz. output coding the cs5525/26 output data in binary format when operating in unipolar mode and in two's comple- ment when operating in bipolar mode. the output conversion word is 24 bits, or three bytes long, as shown in table 5. the msb is output first followed by the rest of the data bits in descend- ing order. for the cs5525 the last byte is composed of bits d7-d4, which are always logic 1; d3-d2, which are always logic 0; and bits d1-d0 which are the two flag bits. for the cs5526 the last byte in- cludes data bits d7-d4, d3-d2 which are always logic 0 and the two flag bits. the of (overrange flag) bit is set to a logic 1 any time the input signal is: 1) more positive than posi- tive full scale, 2) more negative than zero (unipolar mode), 3) more negative than negative full scale (bipolar mode). it is cleared back to logic 0 when- ever a conversion word occurs which is not over- ranged. the od (oscillation detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. this does not occur under normal oper- ating conditions, but may occur whenever the input xout xin cs5525 cs5526 500 k w 20 pf 32.768 khz va+ vd+ figure 18. surface mount crystal connection diagram figure 19. filter response (normalized to output word rate = 1) table 5. data conversion word output conversion data cs5525 (16 bits + flags) output conversion data cs5526 (20 bits + flags) d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb1413121110987654321lsb111100odof d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb181716151413121110987654321lsb00odof
cs5525 cs5526 ds202f1 23 to the converters is extremely overranged. if the od bit is set, the conversion data bits can be completely erroneous. the od flag bit will be cleared to logic 0 when the modulator becomes stable. table 6 illus- trates the output coding for the cs5525/26. power consumption the cs5525/26 accommodate four power con- sumption modes: normal, low power, standby, and sleep. the normal mode, the default mode, is en- tered after a power-on-reset and typically con- sumes 7.5 mw. the low power mode is an alternate mode that reduces the consumed power to 4 mw. it is entered by setting bit d16 (the low power mode bit) in the configuration register to logic 1. since the converters noise performance improves with increased power consumption, slightly degraded noise or linearity performance should be expected in the low power mode. the final two modes are re- ferred to as the power save modes. they power down most of the analog portion of the chips and stop filter convolutions. the power save modes are entered whenever the ps/r bit and the cb bit of the command word are set to logic 1. the particular power save mode entered depends on state of bit d4 (the power save select bit) in the configuration register. if d4 is logic 0, the converters enters the standby mode reducing the power consumption to 1.2mw. the standby mode leaves the oscillator and the on-chip bias generator running. this allows the converters to quickly return to the normal or low power mode once the ps/r bit is set back to a logic 1. if d4 in the configuration register and cb and ps/r in the command word are set to logic 1, the sleep mode is entered reducing the consumed power to less than 500 w. since the sleep mode disables the oscillator, approximately a 500ms os- cillator start-up delay period is required before re- turning to the normal or low power mode. pcb layout the cs5525/26 should be placed entirely over an analog ground plane with both the agnd and dgnd pins of the device connected to the analog plane. place the analog-digital plane split immedi- ately adjacent to the digital portion of the chip. note: vfs in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. see text about error flags under overrange conditions. unipolar input voltage offset binary bipolar input voltage two's complement unipolar input voltage offset binary bipolar input voltage two's complement >(vfs-1.5 lsb) ffff >(vfs-1.5 lsb) 7fff >(vfs-1.5 lsb) fffff >(vfs-1.5 lsb) 7ffff vfs-1.5 lsb ffff ----- fffe vfs-1.5 lsb 7fff ----- 7ffe vfs-1.5 lsb fffff ----- ffffe vfs-1.5 lsb 7ffff ----- 7fffe vfs/2-0.5 lsb 8000 ----- 7fff -0.5 lsb 0000 ----- ffff vfs/2-0.5 lsb 80000 ----- 7ffff -0.5 lsb 00000 ----- fffff +0.5 lsb 0001 ----- 0000 -vfs+0.5 lsb 8001 ----- 8000 +0.5 lsb 00001 ----- 00000 -vfs+0.5 lsb 80001 ----- 80000 <(+0.5 lsb) 0000 <(-vfs+0.5 lsb) 8000 <(+0.5 lsb) 00000 <(-vfs+0.5 lsb) 80000 table 6. 5525/26 output coding cs5525 16-bit output coding cs5526 20-bit output coding
cs5525 cs5526 24 ds202f1 pin descriptions clock generator xin; xout - crystal in; crystal out, pins 9, 10. a gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be supplied into the xin pin to provide the master clock for the device. control pins and serial data i/o cs - chip select, pin 18. when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. sdi - serial data input, pin 17. sdi is the input pin of the serial input port. data will be input at a rate determined by sclk. sdo - serial data output, pin 14. sdo is the serial data output. it will output a high impedance state if cs = 1. sclk - serial clock input, pin 11. a clock signal on this pin determines the input/output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. a0, a1, a2, a3 - logic outputs, pin 6, 7, 15, 16. the logic states of a0-a3 mimic the states of the d20-d23 bits of the configuration register. logic output 0 = agnd, and logic output 1 = va+. 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 10 11 analog ground agnd vref+ voltage reference input positive analog power va+ vref- voltage reference input differential analog input ain+ cs chip select differential analog input ain- sdi serial data input negative bias voltage nbv a3 logic output logic output a0 a2 logic output logic output a1 sdo serial data output charge pump drive cpd vd+ positive digital power crystal in xin dgnd digital ground crystal out xout sclk serial clock input
cs5525 cs5526 ds202f1 25 measurement and reference inputs ain+, ain- - differential analog input, pins 3, 4. differential input pins into the device. vref+, vref- - voltage reference input, pins 20, 19. fully differential inputs which establish the voltage reference for the on-chip modulator. nbv - negative bias voltage, pin 5. input pin to supply the negative supply voltage for the 20x gain instrumentation amplifier. may be tied to agnd if ain+ and ain- inputs are centered around +2.5 v; or it may be tied to a negative supply voltage (-2.1 v typical) to allow the amplifier to handle low level signals more negative than ground. cpd - charge pump drive, pin 8. square wave output used to provide energy for the charge pump. power supply connections va+ - positive analog power, pin 2. positive analog supply voltage. nominally +5 v. vd+ - positive digital power, pin 13. positive digital supply voltage. nominally +3.0 v or +5 v. agnd - analog ground, pin 1. analog ground. dgnd - digital ground, pin 12. digital ground.
cs5525 cs5526 26 ds202f1 specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin.). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs. spi? is a trademark of motorola inc., microwire? is a trademark of national semiconductor corp. ordering guide model number linearity error (max) temperature range package cs5525-ap 0.003% -40 c to +85 c 20-pin 0.3" plastic dip cs5525-as 0.003% -40 c to +85 c 20-pin 0.2" plastic ssop cs5526-bp 0.0015% -40 c to +85 c 20-pin 0.3" plastic dip cs5526-bs 0.0015% -40 c to +85 c 20-pin 0.2" plastic ssop
cs5525 cs5526 ds202f1 27 notes: 1. positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e does not include mold flash. inches millimeters dim min max min max a 0.155 0.180 3.94 4.57 a1 0.020 0.040 0.51 1.02 b 0.015 0.022 0.38 0.56 b1 0.050 0.065 1.27 1.65 c 0.008 0.015 0.20 0.38 d 0.960 1.040 24.38 26.42 e 0.240 0.260 6.10 6.60 e 0.095 0.105 2.41 2.67 ea 0.300 0.325 7.62 8.25 l 0.125 0.150 3.18 3.81 0 15 0 15 20 pin plastic (pdip) package drawing e d seating plane b1 e b a l a1 top view bottom view side view 1 ea c
cs5525 cs5526 28 ds202f1 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.272 0.295 6.90 7.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 l 0.025 0.040 0.63 1.03 0 8 0 8 20 pin ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 29 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5525 cdb5526 cdb5525/26 evaluation board and software features l direct thermocouple interface l rs-232 serial communication with pc l on-board 80c51 microcontroller l on-board voltage reference l lab windows/cvi tm evaluation software - register setup & chip control - fft analysis - time domain analysis - noise histogram analysis l on-board charge pump drive circuitry l integrated rs-232 test mode general description the cdb5525/26 is an inexpensive tool designed to evaluate the performance of the cs5525 and cs5526, 16-bit and 20-bit multi-range analog-to-digital convert- ers (adc). the evaluation board includes an lt1019 voltage refer- ence, an 80c51 microcontroller, an rs232 driver/receiver, and firmware. the 8051 controls the se- rial communication between the evaluation board and the pc via the firmware, thus, enabling quick and easy access to all of the cs5525/26s registers. the cdb5525/26 also includes software for time do- main analysis, histogram analysis, and frequency domain analysis. ordering information: cdb5526 nbv drive circuitry ref+ ain+ ain- ref- j1 -5 analog +5 analog agnd dgnd +5 digital voltage reference crystal 32768hz cs5526 ain+ ain- nbv xin xout cs sdi sdo sclk test switches off on 1 2 3 80c51 microcontroller rs232 driver/receiver rs232 connector leds reset circuitry crystal 11.0592mhz a3 a2 a1 a0 hdr6 cpd jan 98 ds202db5
cdb5525 cdb5526 30 ds202db5 part i: hardware introduction the cdb5525/26 evaluation board provides a quick means of testing the cs5525 and cs5526 analog-to-digital converters (adcs). the board interfaces the cs5525/26 to an ibm tm compatible pc via an rs-232 interface while operating from a +5v and -5v power supply. to accomplish this, the board comes equipped with an 80c51 microcon- troller and a 9-pin rs-232 cable physically inter- faces the evaluation board to the pc. additionally, analysis software provides easy access to the inter- nal registers of the converter, and provides a means to display the converters time domain, frequency domain, and noise histogram performance. evaluation board overview the board is partitioned into two main sections: an- alog and digital. the analog section consists of the cs5525 or the cs5526, a precision voltage refer- ence, and the circuitry to generate a negative volt- age. the digital section consists of the 80c51 microcontroller, the hardware test switches, the re- set circuitry, and the rs-232 interface. the cs5525/26 is designed to digitize low level signals while operating from a 32.768 khz crystal. as shown in figure 1, a thermocouple can be con- nected to the converters inputs via j1s ain+ and ain- inputs. note, a simple rc network filters the thermocouples output to reduce any interference picked up by the thermocouple leads. the evaluation board provides two voltage refer- ence options, on-board and external. with hdr5s jumpers in positions 1 and 4, the lt1019 provides 2.5 volts (the lt1019 was chosen for its low drift, typically 5ppm/c). by setting hdr5s jumpers to position 2 and 3, the user can supply an external voltage reference to j1s ref+ and ref- inputs (application note 4 in the back of the 1995 crystal semiconductor data acquisition databook details various voltage references). the adc serial interface is spi tm and microwire tm compatible. the interface control lines (cs , sdi, sdo, and sclk) are connected to the 80c51 microcontroller via port one. to inter- face an external microcontroller, these control lines are also connected to hdr6. however to accom- plish this, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the microcontroller, 2) remove resistors r1-r8, or 3) remove the microcontroller. figure 2 illustrates the schematic of the digital sec- tion. it contains the microcontroller, a motorola mc145407 interface chip, and test switches. the test switches aid in debugging communication problems between the cdb5525/26 and the pc. the microcontroller derives its clock from an 11.0592 mhz crystal. from this, the controller is configured to communicate via rs-232 at 9600 baud, no parity, 8-bit data, and 1 stop bit.
cdb5525 cdb5526 ds202db5 31 ref+ ain+ ain- ref- j1 +5v analog c21 0.1 f r18 301 w r17 301 w c2 4700pf hdr5 c3 0.68f c4 0.68f 3 4 20 19 hdr1 hdr2 1,lt1019 2,ref+ 3,ref- 4,agnd 1, agnd 2, ain+ 1, ain- 2, agnd 7 c15 0.1f lt1019 2.5v r22 50 w 1 u3 c30 10f c16 0.1f 2 +5v analog r21 10 w 13 c11 0.1f c31 10f 9 10 y2 32768hz va+ agnd ain+ ain- ref+ ref- vd+ xin xout 18 cs 17 sdi 14 sdo 11 sclk 16 a3 15 a2 7 a1 6 a0 12 dgnd to figure 2 5 nbv c29 10f d2 bat85 + u2 lm337_lz r20 1k w r19 1k w c13 0.1f + 1 2 3 adj vout vin c22 1 f + -5v analog 3 3 7 g n d hdr4 d3 1n4148 8 cpd 1 2 c9 0.015 f d5 1n4148 tp70 tp68 u4 cs5526 r16 301 w r15 301 w c1 4700pf hdr3 jp4 jp3 +5v analog jp5 jp6 note: cs5525 and cs5526 are interchangeable cpd c p d do3 do2 do1 do0 figure 1. analog schematic section
cdb5525 cdb5526 32 ds202db5 cs r1 1 200 w sdi r2 2 200 w sdo r3 3 200 w sclk r4 4 200 w do3 r5 5 200 w do2 r6 6 200 w do1 r7 7 200 w do0 r8 8 200 w 18 y1 11.0592mhz 19 c23 33pf c0g c24 33pf c0g 9 +5v digital 40 +5v digital 39 r13 10k w + 1 8 + 2 7 + 3 6 + 4 5 r12 5.11k w r11 5.11k w r10 5.11k w 14 13 12 11 10 c7 47 f c17 0.1f + test switch 1 test switch 2 test switch 3 21 22 23 24 s1 d1 led_555_5003 reset comm gaincal offsetcal jp2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 xtal1 xtal2 c19 0.1f bypass cap reset +5v digital r9 750k w c18 0.1f d4 1n4148 rst vss 20 vdd p0.0 p3.0 p3.1 p3.2 p3.3 p3.4 p2.0 p2.1 p2.2 p2.3 from rs-232 txd rxd tp71 tp72 16 15 14 13 12 11 normal loopback c28 10f + 24 u1 mc145407 c27 10f + 3 1 c25 10f + 18 20 5 6 7 8 9 10 c2- c2+ c1- c1+ vcc vdd 17 +5v digital c26 10f + r14 10k w 5 6 7 8 4 1 9 3 2 ri txd rxd rts cts dtr dsr dcd um1 80c51 from figure 1 do3 do2 do1 do0 cs sdi sdo sclk hdr6 to rs-232 hdr7 figure 2. digital schematic section
cdb5525 cdb5526 ds202db5 33 table 1 lists the rs-232 commands used to com- municate between the pc and the microcontroller. to develop additional code to communicate to the evaluation board via rs-232, the following ap- plies: to write to an internal adc register, choose the appropriate write command byte (see table 1), and transmit it lsb first. then, transmit the three data bytes lowest order byte (bits 7-0) first with the lsb of each byte transmitted first. these three data bytes provide the 24-bits of information to be written to the desired register. to read from an in- ternal register, choose the appropriate read com- mand byte and transmit it lsb first. then, the micro controller automatically acquires the adcs register contents and returns the 24-bits of informa- tion. the returned data is transmitted lowest order byte first with the lsb of each byte transmitted first. figure 3 illustrates the power supply connections to the evaluation board. the +5v analog supplies the analog section of the evaluation board, the lt1019 and the adc. the -5v analog supplies the nega- tive bias voltage circuitry. the +5v digital sup- plies a separate five volts to the digital section of the evaluation board, the 80c51, the reset circuitry, and the rs-232 interface circuitry. using the evaluation board the cs5525/26 are highly integrated adcs. they contain an instrumentation amplifier (ia), a pro- grammable gain amplifier (pga), an on-chip charge pump drive (cpd), and programmable out- put word rates (owr). the ia provides a set gain of 20 while the pga sets the input levels of the adc at either 25 mv, 55 mv, 100 mv, 1 v, 2.5 v, or 5 v (for vref = 2.5 v). the cpd provides a square wave output. this output is used to supply the negative supply to the ia, enabling measure- ments of ground referenced signals. the adcs digital filter allows the user to select output word rates (owrs) from 3.76 hz up to 202 hz. 606 hz output word rates can be attained when a 100khz clock source is used. since the cs5525/26 have such a high degree of integration and flexibility, the cs5525/26 data sheet should be read thoroughly before and consulted during the use of the cdb5525/26. register read command byte write command byte offset register 0x90 (h) 0x80 (h) gain register 0x92 (h) 0x82 (h) configuration register 0x94 (h) 0x84 (h) conversion data register 0x96 (h) --- table 1. microcontroller command via rs-232 +5v analog -5v analog z2 p6ke6v8p + c6 47 f c20 0.1f z3 p6ke6v8p + c5 47f c14 0.1f +5v digital z1 p6ke6v8p + c8 47f c12 0.1f +5v analog -5v analog +5v digital agnd dgnd figure 3. power supplies
cdb5525 cdb5526 34 ds202db5 negative bias voltage the evaluation board provides three means of sup- plying the negative bias voltage (nbv). hdr4 selects between them. when hrd4 is in position one, the lm337 supplies nbv with an adjustable voltage. r19 is used to adjust this voltage between -1.25 v and -5 v. when in position two, hdr4 grounds nbv. and by setting hdr4 to position three, the converters charge pump drive provides nbv with a dc rectified voltage, nominally -2.1 v. note: nbv should not exceed a voltage more negative than -3.0 v. software the evaluation board comes with software and an rs-232 cable to link the evaluation board to the pc. the executable software was developed with lab windows/cvi tm and meant to run under win- dows tm 3.1 or later. after installing the software, read the readme.txt file for last minute changes in the software. additionally, part ii: software fur- ther details how to install and use the software. ibm, at and ps/2 are trademarks of international busi- ness machines corporation. windows is a trademark of microsoft corporation. lab windows and cvi are trademarks of national instruments. spi tm is a trademark of motorola. microwire tm is a trademark of national semicon- ductor. name function description hdr1 used to switch ain+ between j1 input and agnd. hdr2 used to switch ain- between j1 input and agnd. hdr3 used in conjunction with hdr4 to switch the power for nbv from the lm337, cpd or analog ground. hdr4 used in conjunction with hdr3 to switch the power for nbv from the lm337, cpd or analog ground. hdr5 used to switch vref+ and vref- pins from external j1 connection header to the on board lt1019 refer- ence. hdr6 used to connect external micro-con- troller. hdr7 used in conjunction with the self test modes to test the uart communica- tion between the microcontroller and the pc.
cdb5525 cdb5526 ds202db5 35 part ii: software installation procedure to install the software: 1) turn on the pc. 2) at dos prompt type win to launch windows 3.1 tm or later. 3) insert the installation diskette into the pc. 4) from within the windows program manager, pull down file from the menu bar and select the run option. 5) at the prompt type: a:\setup.exe . 6) the program will begin installation. 7) after a few seconds, the user will be prompted to enter the directory in which to install the cvi run-time engine tm . the run-time en- gine tm manages executable created with lab windows/cvi tm and takes approximately 1.5 megabytes of hard drive space. if the default directory is acceptable, select ok and the run- time engine tm will be installed there. 8) after the run-time engine tm is installed, the user is prompted to enter the directory in which to install the cdb5525/26 software. select ok to accept the default directory. 9) the program takes a few minutes to install. af- ter the program is installed, double click on the eval5526 icon to launch it. after a few seconds, the user should be in the cs5525/26 environ- ment. note: the software is written to run with 640 x 480 (standard vga in windows 3.1 tm ) resolution; however, it will work with 1024 x 768 resolution. if the user inter- face seems to be a little small, the user might consider setting the display settings to the 640 x 480 standard (640x480 was chosen to accommodate a variety of computers). using the software at start-up, the window start-up configu- ration appears first. this window contains in- formation concerning the softwares title, revision number, copyright date, etc. additionally, at the top of the screen is a menu bar which displays user options. notice, the menu bar item menu is initial- ly disabled. this eliminates any conflicts with the mouse or concurrent use of modems. before pro- ceeding any further, the user is prompted to select the serial communication port. to initialize a port, pull down option setup from the menu bar and se- lect either com1 or com2. after a port is initial- ized, it is a good idea to test the rs-232 link between the pc and the evaluation board. to do this, pull down the setup menu from the menu bar and select the option testrs232. the user is then prompted to set the evaluation boards test switches to 011 and then reset the board. once this is done, proceed with the test. if the test fails, check the hardware connection and repeat again. otherwise, set the test switches to 000 (normal mode) and reset the board. the option menu is now available and performance tests can be executed. the evaluation software provides three types of analysis tests - time domain, frequency domain, and histogram. the time domain analysis pro- cesses acquired conversions to produce a plot of conversion sample number versus magnitude. the frequency domain analysis processes ac- quired conversions to produce a magnitude versus frequency plot using the fast-fourier transform (results up to fs/2 are calculated and plotted). also, statistical noise calculations are calculated and dis- played. the histogram analysis test processes ac- quired conversions to produce a histogram plot. statistical noise calculations are also calculated and displayed (see figures 4 through figure 9). the evaluation software was developed with lab windows/cvi tm , a software development package from national instruments. more sophisticated
cdb5525 cdb5526 36 ds202db5 analysis software can be developed by purchasing the development package from national instru- ments (512-794-0100). menu bars overview the menu bar controls the link between windows and allows the user to exit the program. it also al- lows the user to initialize the serial port and load presaved data conversions from a file. the five principal windows are the start up configu- ration (also referred to as the setup window), the input / output window, the histogram win- dow, the power spectrum window (also referred to as the fft window), and the time domain win- dow. specifically, the menu bar has the following control items: menu: to select, click on option menu from the menu bar, or use associated hot keys. the items as- sociated with menu are listed and described below. setup window (f1) input/output window (f2) histogram window (f3) power spectrum window (f4) time domain window (f5) these five menu items allow the user to navigate between the five windows. they are available at all times via the menu bar or hot keys. setup: to select, click on option setup from the menu bar. the functions available under setup are: com1: when selected, com1 is initialized to 9600 baud, no parity, 8 data bits, and 1 stop bit. com2: when selected, com2 is initialized to 9600 baud, no parity, 8 data bits, and 1 stop bit. load from disk: used to load and display previ- ously saved data conversions from a file. the file must comply with the cdbcapture file save format. the format is: part number, throughput (or sample rate), number of con- versions, maximum range, and the data con- versions. the user is prompted to enter the path and file name of previously saved data. to prevent hardware conflicts, this option is deactivated while in the input/output win- dow. testrs232: this test mode tests the ability of the pc to communicate to the evaluation board. it consists of two subtests: 1) test the link be- tween the pc and the rs-232 interface cir- cuitry; and 2) test the rs-232 link between the pc and the microcontroller. hdr7 dis- tinguishes these two subtests. set hdr7 to normal to test the complete communication link. or set hdr7 to loop back to test the link between the rs-232 circuitry and the pc. then, set the test switches to 110 and re- set the evaluation board. the leds should indicate a binary six signifying that the hard- ware is ready to initiate the test. to complete the test, the user must initialize the pc. first, use the setup menu to select a communica- tions port and then select the testrs232 op- tion. from there, user prompts navigate the user through the test. the pc indicates if the test passes or fails. once either test is com- plete, the leds toggle to indicate that the test mode is complete. part: allows user to select a different converter. quit: allows user to exit program. input/output window overview the input/output window allows the user to read and write to the internal register of the converter in either binary or hexadecimal, and acquire real-time conversions. it has quick access control icons that quickly reset the converter, reset the converters se- rial port, or self-calibrate the converters offset and
cdb5525 cdb5526 ds202db5 37 gain. the following are controls and indicators as- sociated with this window. acquire: this is a control icon. when pressed, the pc transmits the collect single conversion command to the microcontroller. the microcontroller in turn collects a conversion from the adc and returns it to the pc. the pc stores the conversion and collects additional conversions to form a set. from the sam- ple set collected, the high, the low, peak-to-peak, av- erage, and standard deviation, are computed (the size of the data set is set by the num to average in- put) and then the display icons are updated. this process continues until the stop button is pressed, or until another window is selected. note: the quick access control icons are disabled once acquire is selected. this eliminates potential hardware con- flicts. binary: input icons set or clear the 24 individual bits in the gain, configuration, or offset registers. the bits are first set, then the control icon write all registers is selected to update the registers in the converter. configuration register: text display box that displays the decoded meaning of each bit in the configuration register. decimal: three display icons that display in decimal the contents of the gain, configuration, and offset registers. digital output: display icon that displays the four states of the output latch. gain register: display icon that displays the decimal equivalent of the bits set in gain register. hex: three input/display icons that allow a user to set the 24 bits in the gain, configuration, or offset registers via 6 hexadecimal nibbles. if the upper nibbles in the registers are zeros, then leading zero nibbles need to be entered. num to average: input icon that sets the size of the data conversion set referred to when the ac- quire button is pressed. read all registers: this is a control icon. when pressed the gain, offset, and configuration registers contents are acquired. then, the configuration text box and the register content icons are updated. reinitialize: this is a control icon. when pressed, 128 logic 1s followed by a logic 0 are sent to the adcs serial port to reset its port. it does not reset the rs-232 link. reset a/d: this is a control icon. when pressed, the microcontroller sends the appropriate com- mands to return the converter to its initial default state. self calibrate: this is a control icon. when pressed, the appropriate commands are sent to the adc to calibrate its own offset and gain. stop: stops the collection of conversion data. write all registers: this is a control icon. when pressed, the 72 binary input icons settings are ac- quired. this data is then transmitted to the adcs gain, offset, and configuration registers. then, the pcs display is updated to reflect the registers changes.
cdb5525 cdb5526 38 ds202db5 histogram window overview the following is a description of the controls and in- dicators associated with the histogram window. many of the control icons are usable from the histo- gram window, the frequency domain window, and the time domain window. for brevity, they are only described in this section. bin: displays the x-axis value of the cursor on the histogram. cancel: once selected, it allows a user to exit from the collect algorithm. if data conversion sample sets larger than 64 are being collected and the cancel button is selected, it is recommended that the user reset the evaluation board. the board will eventually recover from the continuous collec- tion mode, but the recovery time could be as long as 10 minutes. collect: initiates the data conversion collec- tion process. collect has two modes of opera- tion: collect from file or collect from converter. to collect from a file an appropriate file from the set- up-disk menu bar option must be selected. once a file is selected, its content is displayed in the graph. if the user is collecting real-time conver- sions to analyze, the appropriate com port must be selected. the user is then free to collect the preset number of conversions (preset by the config pop-up menu discussed below). notice, there is a significant acquisition time difference in the two methods. config: opens a pop-up panel to configure how much data is to be collected, and how to process the data once it is collected. the following are controls and indicators associated with the config panel. samples: user selection of 64, 256, 512, 1024, 2048, 4096, or 8192 conver- sions. window: used in the power spectrum win- dow to calculate the fft. window- ing algorithms include the blackman, blackman-harris, hann, 5-term hodie, and 7-term hodie. the 5-term hodie and 7- term hodie are windowing algo- rithms developed at crystal semi- conductor. if information concerning these algorithms is needed, call technical support. average: sets the number of consecutive ffts to perform and average. limited noise bandwidth: limits the amount of noise in the converters bandwidth. default is 0 hz. ok: accept the change magnitude: displays the y-axis value of the cursor on the histogram. maximum: indicator for the maximum value of the collected data set. mean: indicator for the mean of the data sample set. minimum: indicator for the minimum value of the collected data set. output: control that calls a pop-up menu. this menu controls three options: 1) save current data set to a file with the cdbcapture format, 2) print current screen, or 3) print current graph. restore: restores the display of the graph after zoom has been entered. std. dev.: indicator for the standard deviation of the collected data set. test: quick access control icon, similar to the hot keys, to allow user to quickly switch between a time domain, a frequency domain, or a histogram display. variance: indicates the variance for the cur- rent data set.
cdb5525 cdb5526 ds202db5 39 zoom: control icon that allows the operator to zoom in on a specific portion of the current graph. to zoom, click on the zoom icon, then click on the graph to select the first point (the 1st point is the top left corner of the zoom box). then click on the graph again to select the second point (the 2nd point is the bottom right corner of the zoom box). once an area has been zoomed in to, the output functions can be used to print a hard copy of that region. click on restore when done with the zoom function. frequency domain window (i.e. fft) the following describe the controls and indicators associated with the frequency domain window . cancel: see description in histogram window overview . collect: see description in histogram win- dow overview . config: see description in histogram window overview . frequency: displays the x-axis value of the cursor on the fft display. magnitude: displays the y-axis value of the cursor on the fft display. output: see description in histogram window overview . s/d: indicator for the signal-to-distortion ratio, 4 harmonics are used in the calculations (decibels). s/n+d: indicator for the signal-to-noise + distor- tion ratio (decibels). snr: indicator for the signal-to-noise ratio, first 4 harmonics are not included (decibels). s/pn: indicator for the signal-to-peak noise ratio (decibels). test: see description in histogram window overview . zoom: see description in histogram window overview . # of avg: displays the number of ffts averaged in the current display. time domain window overview the following controls and indicators are associat- ed with the time domain window . cancel: see description in histogram window overview . collect: see description in histogram win- dow overview . config: see description in histogram window overview . count: displays current x-position of the cursor on the time domain display. magnitude: displays current y-position of the cursor on the time domain display. maximum: indicator for the maximum value of the collected data set. minimum: indicator for the minimum value of the collected data set. output: see description in histogram window overview . test: see description in histogram window overview . zoom: see description in histogram window overview. trouble shooting the evaluation board this section describes special test modes incorporated in the microcontroller software to diagnose hardware problems with the evaluation board. note: to enter these modes, set the test switches to the appropriate position and reset the evaluation board. to re- enter the normal operation mode, set the switches back to binary zero and reset the board again. test mode 0, normal mode: this is the default mode of operation. to enter this mode, set the test
cdb5525 cdb5526 40 ds202db5 switches to 000 and reset the board. the evaluation board allows normal read/writes to the adcs reg- isters. all the leds toggle on then off after reset, and then only when communicating with the pc. test mode 1, loop back test: this test mode checks the microcontrollers on-chip uart. to enter this mode, set test switches to 001, set hdr7 for loop back, and then reset the board. if the com- munication works, all the led's toggle. otherwise, only 1/2 of the leds toggle to indicate a commu- nication problem. test mode 2, read/write to adc: this test mode tests the microcontrollers ability to read and write to the adc. to enter this mode, set the switches to 010 and reset the board. in this test mode, the adcs configuration, offset, and gain registers are written to and then read from. if the correct data is read back, all the led's toggle. otherwise, only half of them toggle to indicate an error. test mode 3, continuously acquire single con- version: this test mode repetitively acquires a sin- gle conversion. to enter this mode, set the test switches to 011 and press reset. a binary three is in- dicated on the leds. by probing hdr6 and using cs as a triggering pin, an oscilloscope or logic an- alyzer will display in real-time how the microcon- troller reads conversion data. test mode 4: reserved for future modifications. test mode 5, continuously read gain register: this test mode repetitively acquires the gain regis- ters default contents (0x800000 hex). to enter this mode, set the test switches to 101 and press re- set. the leds should indicate a binary five. by probing hdr6 and using cs as a triggering pin, an oscilloscope or logic analyzer will display in real- time how the microcontroller acquires a conver- sion. test mode 6, pc to microcontroller rs-232 communication link test: this test mode tests the ability of the pc to communicate to the evalua- tion board. it consists of two subtests: 1) test the link between the pc and the rs-232 interface cir- cuitry; and 2) test the rs-232 link between the pc and the microcontroller. hdr7 distinguishes these two subtests. set hdr7 to normal to test the com- plete communication link. or set hdr7 to loop back to test the link between the rs-232 circuitry and the pc. then, set the test switches to 110 and reset the evaluation board. the leds should indi- cate a binary six signifying that the hardware is ready to initiate the test. to complete the test, the user must initialize the pc. first, use the setup menu to select a communications port and then se- lect the testrs232 option. from there, user prompts navigate the user through the test. the pc indicates if the test passes or fails. once either test is complete, the leds toggle to indicate that the test mode is complete. test mode 7, toggle leds: this test mode tests the evaluation board leds. to enter this mode, set the test switches to 111 and reset the board. if the mode passes, the leds toggle. note: remember, to return to the normal operating mode, set the test switches to binary zero, return hdr7 to normal, and reset the evaluation board .
cdb5525 cdb5526 ds202db5 41 figure 4. main menu figure 5. input/output window
cdb5525 cdb5526 42 ds202db5 figure 6. frequency domain analysis figure 7. configuration menu
cdb5525 cdb5526 ds202db5 43 figure 8. time domain analysis figure 9. histogram analysis
cdb5525 cdb5526 44 ds202db5 figure 10. cdb5525/26 component side silkscreen
cdb5525 cdb5526 ds202db5 45 figure 11. cdb5525/26 component side (top)
cdb5525 cdb5526 46 ds202db5 figure 12. cdb5525/26 solder side (bottom)
? notes ?

▲Up To Search▲

Price & Availability of CS552526

	To Download CS552526 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .